Yields, performances and reliability of Gallium Arsenide pseudomorphic high electron mobility transistor-based devices are limited by inconsistencies, gate leakage current levels and breakdown voltages. A conventional method to improve the variations, the leakage current levels and the breakdown voltages is to increase ungated recess dimensions about gate nodes of the devices. However, the increased ungated recess dimensions result in reduced performances, in particular, reduced gains and reduced efficiencies. Conventional double ungated recess dimensions further increase costs due to process complexity.
It would be desirable to implement a transistor with a hole barrier layer.